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The Athlon Idle X Files

..or what your CPU really does when it's not working for you

VCool has a new home

The Athlon/Duron family is not really famous for conserving energy. However it can enter a state with lower power consumption but it seems that it often refuses to do so on your average system.
Traditionally this is done by executing a special HLT instruction when there's nothing else to do - but lets take a look at the AMD docs:

Halt State
When the AMD Duron Processor Model 3 executes the HLT instruction, the processor issues a Halt special cycle to the system bus. The phase-lock loop (PLL) continues to run, enabling the processor to monitor bus activity and provide a quick resume from the Halt state. The processor enters a lower power state if the system logic (Northbridge) disconnects the AMD System Bus in response to the Halt special cycle.

Hmm.. apparently the CPU is waiting for the Northbridge to disconnect the bus before going to sleep. But when does that disconnect happen? Back to the Duron Docs:

Significant power savings of the AMD Duron Processor Model 3 only occurs if the processor is disconnected from the system bus by the Northbridge while in the Halt or Stop Grant state. The Northbridge can optionally initiate a bus disconnect upon the receipt of a Halt or Stop Grant special cycle. The option of disconnecting is controlled by an enable bit in the Northbridge.

So it's the Northbridge that is to blame if power saving does not work then. Let's head over to the VT8371-Northbridge Docs:

Device 0 Offset 52 – S2K Timing Control III .................. RW
The contents of this register are preserved during suspend.
Bits 2-0 have no default value.

7Disconnect Enable When STPGNT Detected
6Write to Read Delay .............. .................. default = 1
5-4Read to Write Delay .......... .................. default = 11b
31ns Skew Between Even / Odd Clock Group For
Data (Strapped from MAB3)
0 Disable .................default if no strap on MAB3
1 Enable
2-0Write Data Delay from SYSDC to CPU Data
Output .......................................... (WrDataDly)

The interesting bit is obviously Bit 7 aka "Disconnect Enable When STPGNT Detected Bit". If this bit is set the Northbridge will disconnect the system bus when it detects the STPGNT state.
However the documentation talks only about the STPGNT state the HLT state isn't mentioned...
Either I've overlooked something here or the Northbridge doesn't really care about the HLT state when it comes to bus disconnecting.
So that leaves us wondering: "How does Software cooling work then?" and "What is that STPGNT state, anyway?"

Again the Duron Docs come to our rescue:

Stop Grant States
The AMD Duron Processor Model 3 enters the Stop Grant state upon recognition of assertion of STPCLK# input. There are two mechanisms for asserting STPCLK# – hardware and software.
The Southbridge can force STPCLK# assertion for throttling to protect the processor from exceeding its maximum case temperature. This is accomplished by asserting the THERM# input to the Southbridge. Throttling asserts STPCLK# for a percentage of a predefined throttling period: STPCLK# is repetitively asserted and deasserted until the THERM# pin is deasserted.
Software can force the processor into the Stop Grant state by accessing ACPI-defined registers typically located in the Southbridge. Software places the processor in C2 by reading the PLVL_2 register in the Southbridge.

Now that's neat! If our CPU doesn't enter the STPGNT voluntarily we can make it an offer it cannot refuse....
All we need to do is to assert the STPCLK# input - and the southbridge is in control of that piece of wire.
Oh well, just what we needed: one more chip getting involved.
Anyway, AMD was nice enough to already tell us what we have to do: "Read the PLVL_2 register, Luke"

Now we just have to find that "PLVL_2" register in the southbridge - a quick glance into the VT82C686 docs reveals:

I/O Offset 14 - Processor Level 2 ...................................... RO
7-0 Level 2 ........................................ always reads 0

Reads from this register put the processor into the
Stop Grant state (the VT82C686A asserts STPCLK#
to suspend the processor). Wake up from Stop Grant
state is by interrupt (INTR, SMI, and SCI).
Reads from this register return all zeros; writes to this
register have no effect.

Finally! We found the end of that chain:

Conclusion

It seems that a simple HLT instruction will halt a Athlon/Duron but it will not put it into a low power mode.
Even if you set the Bus disconnect bit in the Northbridge is not sufficient because the Northbridge will only take action if the CPU is in the STPGNT state - a mere HLT in just enough.
NOTE: the AMD 761 Northbridge has an option for disconnecting the bus on HLT.
To put the CPU into the required STPGNT state you'd have to utilize an ACPI register in the southbridge.

Apparently some OSs and cooling utilities fall short in one or the other category:
Usually the OS has an idle loop and probably uses the ACPI register to put the CPU into STPGNT state but it forgets to set the Bus Disconnect Bit.
This is where a lot of (BIOS-)hacks and tools come into play: They set this infamous Northbridge bit - however if OS doesn't use the APCI register or the tool has it's own idle loop with just the HLT instruction, the CPU just won't cool off.

Solution(s)?

Well the solution is kind of obvious: Get an OS and/or a tool that puts your Athlon or Duron to sleep in the way describes above.
There are plenty of tools available - some work, some work sometimes.
And most of them won't really tell you what they do. That's why I wrote a little (~10K) Utility myself that sets the Northbridge bit and incorporates an idle loop that puts the CPU to sleep using the APCI register on the southbridge.
You can download it here.

One question remains: Why isn't all this enabled by default?

Well during my testing I found out that disconnecting the system bus might affect realtime applications, i.e. applications that use hardware in a time-critical way. For example I noticed that with the bus disconnect enabled a captured video is full of dropped or garbled lines. So this cooling feature comes at a cost - probably that's why they kept it hidden.

There's also a problem with system freeze - Click here for more details.

Disclaimer

Since I do not work for AMD or VIA, all the stuff on this page was gathered reading the available Documentation (PDFs) and using of my puny brain - I might be way off on some points here.
So don't blame me if I got something wrong or you fry your system following these instructions...

Still would love to hear comments and thoughts about this whole Athlon/VIA cooling thingy.
Email me at mpet@bigfoot.de.